Computing devices use memory devices to store data and code for a processor to execute its operations. There are different types of memory devices, which are traditionally used in different contexts. For example, server devices tend to use memory devices that allow increased memory capacity per channel. Thus, memory devices with narrower interfaces tend to be selected for servers. However, such memory devices tend to consume more power, making such configurations less desirable in mobile implementations or other implementations where power consumption is an important consideration. Despite a focus on power for mobile implementations, mobile devices continue to become more capable, and there is an increasing demand for memory devices that have greater memory capacities. Traditionally, increasing capacity using memory devices having wider I/O (input/output) interfaces requires adding more channels, with increases in hardware and cost.
Additionally, transition from one generation of memory device to another has traditionally been expected to have an increase in performance based on an increase in throughput. Performance increases can be the result of doubling the data bus speed. However, to increase the data bus speed requires the memory device to exchange data at a correspondingly increased rate. However, doubling the memory core frequency to match a doubling of data bus speed results in cost increases that are impractical for commodity usage. Another approach is to double prefetch to increase minimum data transfer from each device. Increasing prefetch is a nonissue if per device access granularity multiplied by number of devices on a rank is less than or equal to the cacheline size of the processor (assuming independent memory channels). However, memory technologies are currently reaching a point where doubling the prefetch will exceed the cacheline size per rank for client systems that use x8 devices. Exceeding the cacheline size per rank will result in fewer devices per rank, requiring the increase of the number of channels per memory device die. It will be understood that the convention ‘xN’ (where N is a number) refers to an external data bus interface. Thus, x8 refer to an 8-bit wide interface, and x16 refers to a 16-bit wide interface.
Many low power memory devices have traditionally been designed with wider data bus interfaces (e.g., x16 devices as opposed to traditional x8 devices), which limits data storage capacity per channel, but can be used in more power efficient designs. The difference in bus interfaces provides memory device with the same capacity having different interfaces based on differing implementations. However, such differing implementations traditionally required making two different memory die to allow for the different implementations. Making very similar devices that are slight variations of each other for different implementations can increase design and build costs, as well as cause production and inventory issues.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.